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A 65 nm CMOS Quadrature Balanced Switched-Capacitor Power Amplifier for Full- and Half-Duplex Wireless Operation
IEEE Journal of Solid-State Circuits  (IF5.013),  Pub Date : 2021-08-19, DOI: 10.1109/jssc.2021.3101987
Nimrod Ginzberg, Dror Regev, Rani Keren, Emanuel Cohen

This article proposes a multi-mode wireless transmitter for full-duplex (FD) and half-duplex (HD) operation based on a quadrature balanced switched-capacitor power amplifier (QB-SCPA) architecture in 65 nm CMOS. The QB-SCPA provides inherent passive transmit–receive (TX–RX) isolation along with an embedded digital self-interference cancellation (SIC) signal injection mechanism and exhibits excellent TX and RX linearity characteristics. To minimize noise figure degradation to the RX path, local oscillator (LO) signal sharing between the two SCPAs comprising the transmitter and a retiming circuit that generates the 25% clock signals is employed to obtain phase noise suppression at the LNA port. In the FD mode, 50 dB of SIC is demonstrated across the instantaneous bandwidth of a 20 MHz orthogonal frequency-division multiplexing (OFDM) signal with 11 dB peak-to-average power ratio (PAPR), along with −35 dB TX error vector magnitude (EVM) with SIC ON and without digital predistortion. The transmitter achieves a maximum output power of 23 dBm with 26.5% power-added efficiency (PAE) and 21 dBm with 17.4% PAE in HD TX and FD modes, respectively, and has a wide operating bandwidth between 1.5 and 3 GHz.